1. Field of the Invention
The present invention relates to a data retention cell and a data retention method, and more particularly, to a data retention cell and a data retention method based on clock-gating and feedback mechanism.
2. Description of the Prior Art
Lower power consumption has become a big demand for devising integrated circuits mainly due to wide spread use of portable and handheld applications. For instance, battery life is a very important consideration for the performance of handheld devices, and power consumption of handheld devices significantly affects the battery life. In order to reduce power consumption, integrated circuits can be operated in a power-saving mode by switching-off the power during standby operating, which can be done by decoupling either the supply voltage or the ground voltage provided to the integrated circuits.
The transistor used for controlling the coupling situation concerning the supply voltage is usually a PMOS transistor, which is normally termed the header sleep transistor. The transistor used for controlling the coupling situation concerning the ground voltage is usually an NMOS transistor, which is normally termed the footer sleep transistor. Consequently, the supply voltage can be classified into a real supply voltage and a virtual supply voltage, and the ground voltage can be classified into a real ground voltage and a virtual ground voltage. The real supply voltage and the virtual supply voltage are coupled via the header sleep transistor. The real ground voltage and the virtual ground voltage are coupled via the footer sleep transistor.
However, states or data signals of a circuit being stored in flip-flops may be lost in the power-saving mode. Accordingly, various schemes of data-retention circuits have been provided to preserve states or data signals of flip-flops while operating in the power-saving mode for standby operating. Please refer to FIG. 1, which is a conventional data retention cell 100 based on a balloon latch. The data retention cell 100 comprises a master latch unit 102 for receiving an input data signal D, a slave latch unit 106 for outputting an output data signal Q, a switch unit 104, and a balloon latch unit 108. The master latch unit 102 and the slave latch unit 106 function to operate as a master-slave flip-flop. The master latch unit 102 comprises two inverters 141, 142 for latching and three transmission gates 121-123 for controlling data transfer. The slave latch unit 106 comprises two inverters 143, 144 for latching and one transmission gate 124 for controlling data transfer. The switch unit 104 comprises two transmission gates 125, 126 for controlling data transfer. The balloon latch unit 108 comprises two inverters 145, 146 for latching and one transmission gate 127 for controlling data transfer.
The balloon latch unit 108 is powered between the real supply voltage PGVDD and the real ground voltage PGVSS, which means that the balloon latch unit 108 is always powered for preserving data. The virtual supply voltage VDD is coupled to the real supply voltage PGVDD via a header sleep transistor 181 controlled by a sleep signal SLB, and the virtual ground voltage VSS is coupled to the real ground voltage via a footer sleep transistor 182 controlled by a sleep signal SL. The circuit elements excluding the balloon latch unit 108 are powered between the virtual supply voltage VDD and the virtual ground voltage VSS, between the virtual supply voltage VDD and the real ground voltage PGVSS, or between the real supply voltage PGVDD and the virtual ground voltage VSS. The plurality of transmission gates 121-127 are controlled respectively by control clocks CK, CKB and control signals B1, B1B, B2 and B2B. The data retention cell 100 requires an extra balloon latch unit 108 for data-preserving, and furthermore, complicated controlling and timing are required to transfer data signals back and forth between the balloon latch unit 108 and the master-slave flip-flop on any transition from the power-saving mode to the power-active mode or vice verse.